The present invention relates to a semiconductor device and, more particularly, to a non-volatile memory device having a structure where a conductive organic material layer is disposed between upper and lower electrodes and a method for fabricating the same.
A volatile dynamic random access memory (DRAM) device and a non-volatile flash memory device represent two types of memory devices. In the DRAM device, a length of a channel underneath a gate of a cell transistor is adjusted according to a voltage supplied to the gate and a cell capacitor is charged or discharged by electrons moving through the channel formed between source and drain terminals of the cell transistor, so that cell data is read by detecting the charged or discharged state of the cell capacitor. Since the DRAM device is a volatile memory device, when power is not supplied to the device, the cell data stored in the device may be lost due to a leakage current. Thus, the cell capacitor should be continuously charged to maintain the cell data, which increases power consumption.
On the other hand, in a non-volatile flash memory device such as a NAND type flash memory device, Fowler-Nordheim (FN) tunneling is generated due to a voltage supplied to a control gate and a channel region. Then, by FN tunneling, a floating gate is charged with electrons or the electrons are discharged from the floating gate. A threshold voltage of the channel region changes according to the charged or discharged state of the floating gate and the flash memory device distinguishes 0 or 1 data by detecting a change of the threshold voltage. Since the flash memory device uses FN tunneling, the voltage used in the device becomes very high. Furthermore, since a data read/write operation is performed by charging/discharging the electrons in/from the floating gate formed with polysilicon through FN tunneling, a data processing speed becomes slow, i.e., μ-second level.
To fabricate the typical memory device, since at least several tens of processes need to be performed and a memory cell size is relatively great (e.g., 8 F2), it is difficult to highly integrate the device, reduce product cost, and maintain a high yield.
Accordingly, research institutes and enterprises conduct various studies to develop next generation memory devices that overcome limitations of the DRAM and the flash memory devices while keeping their advantages.
Research for the next generation memory devices are being conducted in various fields according to materials used in a unit cell of the devices. For instance, one of the devices applies current into a phase transfer material and detects 0 or 1 data by using resistance difference obtained according to whether the material is cooled to a solid state having less resistance or an amorphous state having greater resistance. Another one of the devices uses the bistable conductive characteristics having high resistance and low resistance in the same voltage when applying a voltage to a conductive organic material. Still another one of the devices uses ferroelectrics. Further still another one of the devices uses a ferromagnetic material having N and S poles to store data. Furthermore, there is study being conducted for a non-volatile memory device employing a planar floating gate using nanocrystals of metal, silicon or compound semiconductor instead of silicon of a flat structure.
However, study groups researching the next generation memory devices have a common problem of finding the optimized process conditions for applying the above materials to the highly integrated memory devices.
Particularly, a non-volatile memory device using a conductive organic material, e.g., a polymer (Po) RAM device, has not been applied to an actual fabrication process and it is not easy to find the precise fabrication conditions. That is, since it is difficult to repetitively form nanocrystals with regular size and distribution in the conductive organic material, a threshold voltage and a bistable conductive characteristic, i.e. Ion/Ioff, become irregular.